Ata to Ultra Ata

ATA to Ultra ATA/66

Advanced ATA Storage Interface

Introduction

Interface History

Understanding the Need for a Faster Disc Interface

Technology Overview

Performance Increase

Cost Stabilization

Backward Compatibility

System Requirements

Data Integrity and Reliability

Conclusions

More Information

Introduction

The PC industry is constantly searching for advanced technology. This equates to more disc space, faster performance, more memory, better displays - virtually every component is under relentless pressure to improve. Continual improvement for the disc drive industry means lower costs, improved reliability, higher capacity, and better performance. As PC performance increases, the performance of the hard drive, which is the central input/output (I/O) device of the PC, becomes increasingly important. Improvement in disc drive performance is a complex area and is measured using several components: seek time, rotational latency, internal transfer rate, cache, and interface speed.

Interface History

The hard drive interface is the path through which data travels between the PC and the hard drive. The original ISA-dependent ATA (IDE) interface was limited to about 4 Mbytes/sec in the beginning, but reached as high as 8 Mbytes/sec. Interface protocols, such as programmed input/output (PIO) and direct memory access (DMA) modes, were designed to take advantage of the new local bus architectures that replaced ISA. ATA interface modes have progressed from PIO to DMA and now Ultra DMA, giving data transfer rates from 8.3, 11.1, and 13.3 Mbytes/sec up to 16.6, 33.3, and now 66.6 Mbytes/sec.

Specification ATA ATA 2 ATA 3 ATA/ATAPI 4 ATA/ATAPI 5

Max Transfer Modes PIO 1 PIO 4

DMA 2 PIO 4

DMA 2 PIO 4

DMA 2

UDMA 2 PIO 4

DMA 2

UDMA 4

Max Transfer Rate 4

Mbytes/sec 16

Mbytes/sec 16

Mbytes/sec 33

Mbytes/sec 66

Mbyte/sec

Max Connections 2 2 2 2 per cable 2 per cable

Cable Required 40-pin 40-pin 40-pin 40-pin 40-pin, 80-conductor

Additional Features - Base - Speed

- Synchronous Transfers - S.M.A.R.T.

- Secure Mode - Queuing

- Overlap

- ATAPI - Speed

- Data Reliability

Year Introduced 1981 1994 1996 1997 1999

The trends in the above chart show that several components have improved with the evolution of the ATA interface. Speed and functionality have made major strides over the years. Performance remains the most commonly considered attribute with interface developments, and Ultra ATA/66 makes burst data transfer rates of up to 66.6 Mbytes/sec possible.

Understanding the Need for a Faster Disc Interface

Ultra ATA/66 provides a low-cost, high-reliability, backwards-compatible solution to data transfer bottlenecks that slow overall system performance. As the data storage density (areal density) of disc drives and rotational speeds have increased, bottlenecks also increased, thus requiring the ATA interface to improve performance to attain compatible data transfer speeds. Potentially, such improvements benefit PC end-users by providing faster PCs -- applications run faster, graphics run more smoothly, and multimedia flows uninterrupted on the screen. Actual performance benefits depend on the total system design and the applications being used. However, the drive performance trend is clear: performance demands on desktop and mobile disc drives will continue to push data transfer rates higher.

Technology Overview

The original ATA interface is based on transistor-transistor logic (TTL) bus interface technology, which is in turn based on the old industry standard architecture (ISA) bus protocol. This protocol uses a data transfer method called asynchronous. Both data and command signals are sent along a signal pulse called a strobe, but the data and command signals are not interconnected. Only one type of signal (data or command) can be sent at a time, meaning a data request must be completed before a command or other type of signal can be sent along the same strobe.

Starting with ATA-2 a more efficient method of data transfer called synchronous is used. In synchronous mode, the drive controls the strobe and synchronizes the data and command signals with the rising edge of each pulse. Synchronous data transfers interpret the rising edge of the strobe as a signal separator. Each pulse of the strobe can carry a data or command signal, allowing data and commands to be interspersed along the strobe. To get improved performance in this environment, it is logical to