Pentium Arcitecture

PENTIUM ARCHITECTURE:

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* REGISTER SET

* INSTRUCTION FORMAT

* ADDRESSING MODES

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REGISTERS:

The processor has 16 registers for use in general systems. These registers can be grouped as:

General purpose data registers:

* Eight registers are available for storing operands and pointers.

* These are EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP.

* These are provided for holding operands for logic and arithmetic operations, operands for address calculations, memory pointers.

* The ESP register should be used very carefully. It holds the stack pointer and generally should not be used for any other purpose.

* There are some special uses of each register:

EAX: Accumulator for operands and result data.

EBX: Pointer to data in the DS segment.

ECX: Counter for string and loop operations.

EDX: I /O pointer

ESI: Pointer to data in the segment pointed to by the DS

register, source pointer for the string operation

EDI: Pointer to data or destination in the segment pointed to by

the ES register.

ESP: Stack pointer

EBP: Pointer to data on the stack (in the SS segment).

These extended 32-bit registers can be separately referred to as two 8-bit registers, so each of the EAX, EBX, ECX, EDX can be referred to as AH, BH, CH, DX (high byte) and AL,BL,CL,DL (low byte).The following figure shows the alternate general purpose register names .

Segment Registers:

* There are segment registers. CS, DS, SS, ES, FS, GS. They hold up to 16-bit segment selectors. A segment selector is a special pointer that identifies a segment in memory.

* To access a particular segment in memory the segment selector for that segment must be present in the appropriate segment register.

* Each of the segment registers is associated with one of the three types of

Storage i.e. code, data or stack.

CS register: Contains the segment selector for the code segment.

DS, BE, ES, GS registers: Contains the segment selector for the data segment.

SS register: Contains the segment selector for the stack segment.

Special Function Registers:

Status and Control Registers:

* These registers report and allow modification of the state of the processor and of the program being executed.

* The EFLAG register contains a group of status flag, a control flag, and a group of system flags

* Some of the flags of the EFLAG register can be modified directly using special-purpose instructions.

* There are no instructions that allow the whole register to be modified directly.

* As the Intel architecture has evolved Flags have been added to the EFLAG register, but the function and placement of the existing flags have remained the same.

* The following figure defines the flags within the EFLAG register.

THE INSTRUCTION FORMAT

The Pentium instruction format is highly complex and irregular. It has six variable-length fields, five of which are optional. The general pattern of the instruction format is shown below:

Prefix byte: The prefix byte is an extra opcode stuck onto the front of an instruction to change its action.

Opcode: The individual bit in the Pentium opcode does not give much information about the instruction. Thus in general, the opcode must be fully decoded to determine what class of operation is to be performed and thus how long the instruction is.

Mode: these 8-bits are split into a 2-bit MOD field and two 3-bit register fields, REG and R/M .Sometimes the first 3-bits of this byte are used as an extension

For the opcode .However, the 2-bit mode field means that there are only four ways to address operands and one of the operands must always be a register. Logically, any of the EAX, EBX, ECX, ESI, EDI, and ESP should be specifiable as either register, but the encoding rules prohibit some combinations and use them for special cases.

SIB: Some modes require an additional byte, called SIB (scale, Index, Base), giving a further specifications. This scheme is not ideal but a compromise given the competing demands of the background compatibility and the desire to add new features not originally envisioned.

Displacement/Immediate: some instruction have 1, 2, or 4 more bytes specifying a memory address (Displacement) and possibly another 1, 2, 4 bytes containing a constant (immediate operand)

ADDRESSING MODES:

The